This is a beginner level course to start learning Systemverilog for IC verification.

Description

The course introduces you to ICverification concepts such as verification flow, importance of verification types of pre-silicon verification and types of stimuli generation.

The course teaches basics of Systemverilog for verification. You will learn data types, operators, interfaces, program control statements, and program block in Systemverilog.

The last part of the course is a case study. You will go through the development of verification environment for a simple sequence detector.

• Verification engineers wishing to develop Systemverilog test bench environments
• Students seeking a job in VLSI industry

Course content

• Introduction
  • Introduction
• Introduction to IC Verification
  • Introduction to IC Verification
  • Importance of IC Verification
  • Types of Pre-Silicon Verification
• Design and Testbench
  • Design and Testbench
  • Types of Stimuli
• SystemVerilog for Verification
  • SystemVerilog
• Datatypes in SystemVerilog
  • Basic Data Types
  • More Basic Data Types
  • User Defined Data Types, Structs and Enumerations
  • Fixed Size Arrays
  • Dynamic Arrays
  • Queues
  • Associative Arrays
  • Array Manipulation Methods
  • Casting
  • Scope and Lifetime
• Operators in SystemVerilog
  • Operators
• Interface
  • Interfaces
  • Modports and Clocking Blocks
• Program Control
  • Initial, Final and Always blocks
  • Selection, Loop and Jump statements
  • Tasks
  • Functions
  • Fork...Join
• Program Block
  • Program Block
• Case Study
  • Case Study
• Summary
  • Summary